Verilog:

module vl_1_bit_adder(C0, A0, B0, C1, S0);
input C0, A0, B0;
output C1, S0;
wire e0, e1, e2, e3;
nand u0(e0, C0, A0);
nand u1(e1, B0, C0);
nand u2(e2, A0, B0);
xnor u3(e3, C0, A0);
nand u4(C1, e1, e2, e0);
xnor u5(S0, B0, e3);
endmodule


VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ===========================================

ENTITY 1_bit_adder IS
  PORT (
    C0 : IN BIT;
    A0 : IN BIT;
    B0 : IN BIT;
    C1 : OUT BIT;
    S0 : OUT BIT
  );
END 1_bit_adder;
-- ===========================================

ARCHITECTURE gate_level OF 1_bit_adder IS

COMPONENT not1 PORT (a1: IN BIT; z: OUT BIT); END COMPONENT;

-- Intermediate nets
  SIGNAL e0, e1, e2, e3 : BIT;

BEGIN
  U0 : nand2 PORT MAP (C0, A0, e0);
  U1 : nand2 PORT MAP (B0, C0, e1);
  U2 : nand2 PORT MAP (A0, B0, e2);
  U3 : xnor2 PORT MAP (C0, A0, e3);
  U4 : nand3 PORT MAP (e1, e2, e0, C1);
  U5 : xnor2 PORT MAP (B0, e3, S0);

END gate_level;